Research/MEMS Power Gate Switch for Low Power Electronics

2019-05-03 (金) 06:39:15 (169d)

低消費電力エレクトロニクスのための集積化MEMS
Integrated MEMS Switch for Low Power Electronics

本研究では、表面マイクロマシニングによるMEMSスイッチを用いて、LSIの待機電力を極限までゼロに近づける新たなパワーゲートスイッチの試作と評価を実施しています。

We propose a new MEMS (Micro Electro Mechanical systems) switch for power gating the LSI processors in order to eliminate the standby leakage and to realize low power operation. Technology scaling has led to higher performance and integration density. However, the sub-threshold leakage increases exponentially as the transistor threshold voltages have been scaled down. Suppression of the leak current is inevitable for low-power mobile electronics. Power-gating switch is a commonly used circuit technique to reduce the leak power, by cutting off the unused part of electronic blocks. Conventional power gating switches use solid-state transistors between the circuit block and the ground network. Transistor switches are simple but have fundamental limitations in their effectiveness. At this point, MEMS switches are expected to eliminate the leak current thanks to the high isolation at the off-state and low resistance at the on-state. We pursue an integrated MEMS approach to build-in the micromechanical power gating switch onto a pre-fabricated CMOS circuitry.

はじめに
Introduction

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半導体エレクトロニクスでは、高速動作と低電圧動作を追求するためにゲート長数十ナノメートルの微細化が進められています。このため、必然的にトランジスタのOFF時のリーク電流が顕在化しつつあります。このリーク電流を低減する方策として、通常は回路ブロックとGND電位の間にパワーゲートスイッチを挿入する手法が一般的でした。しかしながら、パワーゲートスイッチもトランジスタである以上、有限なリーク電流をもっています。

The number of transistors are integrated into a semiconductors chip doubles every two years according to Moore’s Law, LSI has achieved rapid development, now is a lot of transistors integrated on a single circuit. Thanks to the development, portable systems like cell-phones have become extremely popular. However, a system spends most of the time in its standby mode. In a recent article it has been estimated that it spends almost 500 hour in the standby mode and 15 hour in talk time. As a result, the leakage power in the standby mode is especially important issue.

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そこで、このパワーゲートスイッチに相当する部品として、MEMS型の接点開閉スイッチを応用する方法を検討しています。これにより、OFF時のリーク電力をほぼゼロに抑えて、待機時間におけるLSIの消費電力を極力抑制する方法を検討しています。

Common technique for reducing the leakage current is power gating, where the power source to the circuit is shut off by means of a switch. The most common switch is a transistor. Transistor switches are easy to implement and can yield a large leakage reduction, but the transistors themselves have leak current, and the switches have an effective electrical resistance. MEMS switches have good characteristics for ideal power gating switches. The switches have near perfect isolation when off, and almost no resistance when on. In this paper, we propose a MEMS switch for power gating in order to eliminate the leakage current.

スイッチ構造
Switch Structure

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従来のRF−MEMSスイッチでは、高周波におけるインピーダンス整合が設計の制約条件となっており、デバイス寸法が小型化したために、必要な接圧を得るための駆動電圧が高くなる傾向にありました。一方、本研究がめざすパワーゲートスイッチではDC電流を取り扱うため、高周波回路的な設計制約条件がありません。このため、RF−MEMSスイッチよりも大きな面積をアクチュエータ電極に割り当てることが可能であり、駆動電圧を3.3V程度に抑えることも可能です。

Impedance matching has been the limitation in designing the conventional RF-MEMS switches, and hence it usually lead to large drive voltage to make sufficient contact pressure. In our power gating switch, on the other hand, such limitation associated to the RF design does not exist, as it is supposed to handle DC-level voltages. It is, therefore, possible to allocate relatively large footprint for a switch to lower the drive voltage as low as 3.3V.

製作方法
Fabrication Process

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パワーゲートスイッチをLSI基板上に製作することを想定して、低温プロセスでMEMS加工する方法を検討しました。その結果、銅メッキを犠牲層とする金めっきで可動接点構造を製作する方法を研究しています。

We have developed a CMOS-compatible low-temperature process to post-process the power gating switch onto an LSI circuit wafer. An electroplating method has been adopted to construct micromechanical structure of plated gold, while using plated copper as a sacrificial layer.

静電駆動特性予測
Pull-in Voltage Analysis

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3次元有限要素法解析結果により、厚さ1ミクロン程度の有機フィルムを可動メンブレンに用いることで、ブリッジ間隔200ミクロン程度の構造で、3.3V駆動が可能であることが分かりました。

Three-dimensional FEM analysis has discovered that a use of a thin plastic membrane (1 micron) as a suspension would lower the electrostatic operation voltage for the micro bridge structure to be as low as 3.3V.

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